Unitate aritmetica si logica - codul xilinx

Unitate aritmetica si logica

Codul

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

use work.PRIMS. all;

entity ALU is

generic(DEL: TIME:= 5 ns);

port(A,B: in BIT_VECTOR (3 downto 0);

CI: in BIT;

FSEL: in BIT_VECTOR(1 downto 0);

F: out BIT_VECTOR(3 downto 0);

COUT: out BIT);

end entity ALU;

architecture ALG of ALU is

begin

process (A,B,CI,FSEL)

variable FV: BIT_VECTOR(3 downto 0) ;-- ? imaginea rezultatului

variable COUTV: BIT ; --? imaginea bitului de transport

begin

case FSEL is

when '00' => F <=A after DEL ;

when '01' => F <= not A after DEL ;

when '10' => ADD (A, B, CI, FV, COUTV) ;

F <=FV after DEL ;

COUT <= COUTV after DEL ;

when '11' => F <= A and B after DEL;

end case;

end process;

end architecture ALG;

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Codul

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity parity9 is

port (

I: in std_logic_vector (9 downto 1) ;    -- ? o intrare de 9 bi?i

EVEN, ODD:out std_logic);    -- ? doua ie?iri de tip ???

end parity9;

architecture parity9a of parity9 is

begin

process (I)

variable p: std_logic;--? aceasta variabila va con?ine

--indica?ia de paritate: 1 pentru impar, 0 par

begin

p := I(1); --? se cite?te valoarea I(1)

for j in 2 to 9 loop

if I(j) = '1' then p := '1' ; --? se citesc pe rand bi?ii de la

--intrare si se actualizeaz? p

end if;

end loop;

ODD <= p;

EVEN <= not p ; --? ODD si EVEN au valori diferite

end process;

end parity9a;

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