Home - Rasfoiesc.com
Educatie Sanatate Inginerie Business Familie Hobby Legal
Doar rabdarea si perseverenta in invatare aduce rezultate bune.stiinta, numere naturale, teoreme, multimi, calcule, ecuatii, sisteme




Biologie Chimie Didactica Fizica Geografie Informatica
Istorie Literatura Matematica Psihologie

C


Index » educatie » » informatica » C
Sumator pe n biti - Codul programabil


Sumator pe n biti - Codul programabil


Sumator pe n biti

Codul

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.NUMERIC_STD.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity sum_test is

generic (n: natural := 4);



port ( A,B: in std_ulogic_vector (n-1 downto 0);

Cin: in std_ulogic;

Sum: out std_ulogic_vector (n-1 downto 0);

Cout: out std_ulogic);

end sum_test;

architecture sum of sum_test is

signal result : unsigned (n downto 0);

signal carry : unsigned (n downto 0);

begin

carry <= (0=> Cin, others => '0');

result <= ('0'& unsigned (A)) + ('0' & unsigned(B)) + carry;

Sum <= std_ulogic_vector(result(n-1 downto 0));

Cout<= result(n);

end sum;

Afisarea rezultatelor simularii (de tip text)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

USE std.textio.all;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

ENTITY Sum_test_tb_vhd IS

END Sum_test_tb_vhd;

ARCHITECTURE behavior OF Sum_test_tb_vhd IS

file vectors: text; -- se defineste fisierul de intrare

file results: text; -- se defineste fisierul de iesire

-- declarare componenta UUT

COMPONENT sum_test

PORT(

A : IN std_ulogic_vector(3 downto 0);

B : IN std_ulogic_vector(3 downto 0);

Cin : IN std_ulogic;



Sum : OUT std_ulogic_vector(3 downto 0);

Cout : OUT std_ulogic );

END COMPONENT;

----Inputs

SIGNAL Cin : std_logic := '0';

SIGNAL A : std_ulogic_vector(3 downto 0) := (others=>'0');

SIGNAL B : std_ulogic_vector(3 downto 0) := (others=>'0');

--Outputs

SIGNAL Sum : std_ulogic_vector(3 downto 0);

SIGNAL Cout : std_ulogic;

BEGIN

-- Intantiere Unit Under Test (UUT)

uut: sum_test PORT MAP(

A => A,

B => B,

Cin => Cin,

Sum => Sum,

Cout => Cout

tb : PROCESS is

variable ILINE, OLINE: Line; -- declarare variabile

--pointer pententru ctire-scriere

variable X_in, Y_in, Z_out: bit_vector(3 downto 0);

variable ci_in, co_out : bit;

variable ch : character;

BEGIN

file_open (vectors, 'vectori.txt', read_mode);

-- deschidere in mod citire fisier cu vectori de test

file_open (results, 'rezultate.txt', write_mode);

--deschidere in mod scriere fisier cu rezultate simulare

--ciclu de citire-scriere

while not endfile(vectors) loop

readline (vectors, ILINE);-- cite?te o linie din

--fi?ier

read(ILINE, X_in); -- cite?te un vector din

--inie

read(ILINE, ch);

read(ILINE, Y_in);

read(ILINE, ch);

read(ILINE, ci_in);

--converte?te ?i pune stimulii la intrare

A <= to_stdulogicvector(X_in);

B <= to_stdulogicvector(Y_in);

cin <= to_stdulogic(ci_in);

wait for 100 ns;

--cite?te starea ie?irilor

Z_out := to_bitvector (Sum);

co_out := to_bit (cout);

--scrie valorile convertite in fisierul de iesire

write (OLINE, Z_out, right, 5);

write (OLINE, co_out, right, 2);

writeline (results, OLINE);

end loop;

--inchide fisierele

file_close (vectors);

file_close (results);

END PROCESS;

END ARCHITECTURE;








Politica de confidentialitate




Copyright © 2023 - Toate drepturile rezervate