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Memorie ROM 16x8 - Codul de simulare


Memorie ROM 16x8 - Codul de simulare


Memorie ROM 16x8

Codul

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity rom16_8 is

port (address : in std_logic_vector (3 downto 0);

ledg: out std_logic;

data : out std_logic_vector (7 downto 0));

end rom16_8;

architecture Behavioral of rom16_8 is

type rom_array is array (0 to 15) of

std_logic_vector(7 downto 0);

constant rom : rom_array := (

'00000000', --00

'00010001', --11

'00100010', --22

'01000011', --43

'10000100', --84

'01000101', --45

'00100110', --26

'00010111', --17

'00001000', --08

'00011001', --19

'00101010', --2A

'01001011', --4B

'10001100', --8C

'01001101', --4D



'00101110', --2E

'00011111'); --1F

begin

data <= rom(conv_integer(address));

ledg<='1';

end Behavioral;

Fisierul de constrangeri

net 'address(0)' loc='P23';

net 'address(1)' loc='P21';

net 'address(2)' loc='P18';

net 'address(3)' loc='P16';

net 'data(0)' loc='P111';

net 'data(1)' loc='P109';

net 'data(2)' loc='P102';

net 'data(3)' loc='P100';

net 'data(4)' loc='P98';

net 'data(5)' loc='P96';

net 'data(6)' loc='P94';

net 'data(7)' loc='P89';

net 'ledg' loc='P45';

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