Descriere algoritmica pentru un contor de valori 1

Descriere algoritmica pentru un contor de valori 1

Codul

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ONES_CNT is

port (EN: in BIT;

A: in BIT_VECTOR (2 downto 0) ;

C: out BIT_VECTOR (1 downto 0));

end ONES_CNT;

architecture ALGORITHMIC of ONES_CNT is

begin

process(A)

variable NUM: INTEGER range 0 to 3;

begin

if EN = '1' then

NUM := 0;

for I in 0 to 2 loop

if A(I) = '1' then

NUM := NUM + 1;

end if;

end loop;

end if;

case NUM is

when 0 => C <= '00';

when 1 => C <= '01';

when 2 => C <= '10';

when 3 => C <= '11';

end case;

end process;

end ALGORITHMIC;

Afisarea rezultatelor simularii (de tip text)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use STD.TEXTIO.all;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity TEST_BENCH

is end TEST_BENCH;

architecture ONES_CNT1 of

TEST_BENCH is

signal EN: BIT;

signal A: BIT_VECTOR (2 downto 0);

signal C: BIT_VECTOR(1 downto 0) ;

component ONES_CNT

port (EN: BIT;

A: in BIT_VECTOR(2 downto 0);

C: out BIT_VECTOR(1 downto 0) ) ;

end component;

begin

LI: ONES_CNT

port map (EN, A, C);

process

variable VLINE: LINE;

variable V1: BIT_VECTOR(2 downto 0);

variable V2: BIT_VECTOR(1 downto 0);

file INVECT: TEXT is 'TVECT.TXT';

begin

EN <= '0', '1' after 200 ns;

wait on EN until EN = '1';

while not(ENDFILE(INVECT)) loop

READLINE(INVECT, VLINE);

READ(VLINE, V1);

READ(VLINE, V2);

A<= V1;

wait for 100 ns;

assert (V2 = C)

report 'Atentie: C nu este egal cu (V2 sau C)'

severity WARNING;

end loop;

end process;

end ONES_CNT1;