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Cod VHDL pentru setul de registre - laborator


Cod VHDL pentru setul de registre - laborator


Cod VHDL pentru setul de registre

Codul

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity reg16 is

port (A_addr: in std_logic_vector (2 downto 0);

B_addr:in std_logic_vector (2 downto 0);

A_in: in std_logic_vector(7 downto 0);

CLK, LD_reg, WE, BANK_sel, R0A, R0B: in std_logic;

A_out: out std_logic_vector(7 downto 0);

B_out:out std_logic_vector(7 downto 0));

end reg16;

architecture Behavioral of reg16 is

begin

Bank_A: process (CLk) is

type ram_arrayA is array (0 to 7) of

std_logic_vector(7 downto 0);

variable memA: ram_arrayA;

variable A_addr_var : integer;

begin

if clk'event and clk ='1' then

if Bank_sel = '0' then

if R0A ='1' and R0B='1' then

A_addr_var := 0;

else

A_addr_var := Conv_integer (A_addr);

end if;

if WE = '0' then

A_out <= memA(A_Addr_var);

elsif LD_reg = '1' then

memA(A_Addr_var) := A_in;

A_out <= memA(A_Addr_var);

end if;

else null;

end if;

end if;

end process Bank_A;

Bank_B: process (CLk) is

type ram_arrayB is array (0 to 7) of

std_logic_vector(7 downto 0);

variable memB: ram_arrayB;

variable B_addr_var : integer;

begin

if clk'event and clk ='1' then

if Bank_sel = '0' then

if R0A ='1' and R0B='1' then

B_addr_var := 0;

else

B_addr_var := Conv_integer (B_addr);

end if;

if WE = '0' then

B_out <= memB(B_Addr_var);

elsif LD_reg = '1' then

memB(B_Addr_var) := A_in;

B_out <= memB(B_Addr_var);

end if;

else null;

end if;

end if;

end process Bank_B;

end Behavioral;

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