Home - Rasfoiesc.com
Educatie Sanatate Inginerie Business Familie Hobby Legal
Doar rabdarea si perseverenta in invatare aduce rezultate bune.stiinta, numere naturale, teoreme, multimi, calcule, ecuatii, sisteme




Biologie Chimie Didactica Fizica Geografie Informatica
Istorie Literatura Matematica Psihologie

C


Index » educatie » » informatica » C
» Registrul De 16 biti - Xilinx


Registrul De 16 biti - Xilinx


Reg. De 16 biti

Codul

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity reg16bit is

port (CLK, CLKEN, OE_L, CLR_L: in STD_LOGIC;

D: in std_logic_vector (15 downto 0) ;

Q: out std_logic_vector (15 downto 0)) ;

end reg16bit;

architecture regl6bit_beh of reg16bit is

signal CLR, OE: STD_LOGIC;

signal IQ: STD_LOGIC_VECTOR (15 downto 0);

begin

process (CLK, CLR_L, CLR, OE_L, OE, IQ)

begin



CLR <= not CLR_L;

OE <= OE_L;

if (CLR = '1') then IQ <= (others => '0') ;

elsif (CLK'event and CLK='1') then

if (CLKEN = '1') then IQ <= D;

end if;

end if;

if OE = '1' then Q <= IQ;

else Q <= (others => 'Z');-- --ie;ire tristate

end if;

end process;

end architecture;

Afisarea rezultatelor simularii








Politica de confidentialitate




Copyright © 2024 - Toate drepturile rezervate