Home - Rasfoiesc.com
Educatie Sanatate Inginerie Business Familie Hobby Legal
Doar rabdarea si perseverenta in invatare aduce rezultate bune. stiinta, numere naturale, teoreme, multimi, calcule, ecuatii, sisteme


Biologie Chimie Didactica Fizica Geografie Informatica
Istorie Literatura Matematica Psihologie

C


Index » educatie » » informatica » C
Numarator Cu functii de reset si load - Codul in Xilinx


Numarator Cu functii de reset si load - Codul in Xilinx


Numarator Cu functii de reset si load

Codul

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity counter is

port (RESET, LOAD, COUNT, UP, OE, CLK: in std_logic;

DATA_IN: in std_logic_vector( 7 downto 0);

CNT: out std_logic_vector ( 7 downto 0 )) ;

end counter;

use work.PRIMS.all;

architecture ALG of counter is

signal cnt_v : BIT_VECTOR (7 downto 0 );

begin

process(CLK) begin

if CLK'event and CLK='1' then

if RESET = '1' then

cnt_v <= '00000000'; --resetare

elsif LOAD ='1' then

cnt_v <= to_bitvector(DATA_IN); -- conversie din std_logic_vector

--func?ia de incarcare paralela

elsif COUNT ='1' then

if UP = '1' then

-- apelare func?ii descrise in pachetul PRIMS

cnt_v <= INC (cnt_v); --num?rare inainte

else

cnt_v <= DEC (cnt_v);--num?rare inapoi

end if;

end if;

if OE = '1' then -- activare ie?ire

CNT <= to_stdlogicvector( cnt_v); --converise din bit_vector

end if;

end if;

end process;

end ALG;

Afisarea rezultatelor simularii



loading...




Politica de confidentialitate

loading...




Politica de confidentialitate

Copyright © 2020 - Toate drepturile rezervate

Afaceri


Access
Adobe photoshop
Autocad
Baze de date
C
Calculatoare
Corel draw
Excel
Foxpro
Html
Internet
Java
Linux
Mathcad
Matlab
Outlook
Pascal
Php
Powerpoint
Retele calculatoare
Sql
Windows
Word