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Automatul Mealy - Codul si simularea in Xilinx


Automatul Mealy - Codul si simularea in Xilinx


Automatul Mealy

Codul

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Mealy is

port (X, CLOCK: in std_logic;

Z: out std_logic );

end Mealy;

architecture Behavioral of Mealy is

type STATE_TYPE is (S0, S1,S2,S3);

signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;

begin

-- Proces pentru sec?iunea combinationala

COMBIN: process (CURRENT_STATE, X)

begin

case CURRENT_STATE is

when S0 =>

Z<='0' ;

if X ='0' then

NEXT_STATE <= S0;

else

NEXT_STATE <= S2;

end if;

when S1 =>

Z <= '1' ;

if X ='0' then

NEXT_STATE <= S0;

else

NEXT_STATE <= S2;

end if;

when S2 =>

Z <= '1' ;

if X ='0' then

NEXT_STATE <= S2;

else

NEXT_STATE <= S3;

end if;

when S3 =>

Z <= '0' ;

if X ='0' then

NEXT_STATE <= S3;

else

NEXT_STATE <= S1;

end if;

-- toate st?rile curente

end case;

end process COMBIN;

-- Proces pentru sec?iunea secven?iala (bistabile)

SYNCH: process begin

wait until CLOCK'event and CLOCK ='1' ;

CURRENT_STATE <= NEXT_STATE;

end process SYNCH;

end architecture;

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